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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\GaoYun_pro\GW1NR_9C\impl\gwsynthesis\GY_riscv.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>D:\GaoYun_pro\GW1NR_9C\CST\PIN.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.8.06-1</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW1NR-LV9QN88PC6/I5</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW1NR-9C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Aug 08 11:04:31 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 1.14V 85C C6/I5</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.26V 0C C6/I5</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>6466</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>3254</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>2</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>42</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>clk</td>
<td>Base</td>
<td>37.037</td>
<td>27.000
<td>0.000</td>
<td>18.519</td>
<td></td>
<td></td>
<td>clk_ibuf/I </td>
</tr>
<tr>
<td>spi_u0/spi_clk_inter</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter_s1/F </td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>7.937</td>
<td>126.000
<td>0.000</td>
<td>3.968</td>
<td>clk_ibuf/I</td>
<td>clk</td>
<td>u_pll/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>7.937</td>
<td>126.000
<td>0.000</td>
<td>3.968</td>
<td>clk_ibuf/I</td>
<td>clk</td>
<td>u_pll/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>15.873</td>
<td>63.000
<td>0.000</td>
<td>7.937</td>
<td>clk_ibuf/I</td>
<td>clk</td>
<td>u_pll/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>23.810</td>
<td>42.000
<td>0.000</td>
<td>11.905</td>
<td>clk_ibuf/I</td>
<td>clk</td>
<td>u_pll/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>39.683</td>
<td>25.200
<td>0.000</td>
<td>19.841</td>
<td>u_pll/rpll_inst/CLKOUT</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>spi_u0/spi_clk_inter</td>
<td>50.000(MHz)</td>
<td>136.009(MHz)</td>
<td>2</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>25.200(MHz)</td>
<td>33.580(MHz)</td>
<td>8</td>
<td>TOP</td>
</tr>
</table>
<h4>No timing paths to get frequency of clk!</h4>
<h4>No timing paths to get frequency of u_pll/rpll_inst/CLKOUT.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_pll/rpll_inst/CLKOUTP.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_pll/rpll_inst/CLKOUTD.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_pll/rpll_inst/CLKOUTD3.default_gen_clk!</h4>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>spi_u0/spi_clk_inter</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>spi_u0/spi_clk_inter</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;">
<td>1</td>
<td>-5.579</td>
<td>spi_u0/spi_state_s0/Q</td>
<td>spi_u0/mem_rdata_15_s0/D</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.318</td>
<td>0.374</td>
<td>5.093</td>
</tr>
<tr style="color: #FF0000;">
<td>2</td>
<td>-5.438</td>
<td>spi_u0/spi_start_s1/Q</td>
<td>spi_u0/spi_shift_o_7_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>5.700</td>
</tr>
<tr style="color: #FF0000;">
<td>3</td>
<td>-5.170</td>
<td>spi_u0/spi_dir_0_s0/Q</td>
<td>spi_u0/mem_rdata_0_s0/D</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.318</td>
<td>0.374</td>
<td>4.684</td>
</tr>
<tr style="color: #FF0000;">
<td>4</td>
<td>-4.364</td>
<td>spi_u0/spi_state_s0/Q</td>
<td>spi_u0/spi_start_s1/CE</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.318</td>
<td>0.374</td>
<td>4.234</td>
</tr>
<tr style="color: #FF0000;">
<td>5</td>
<td>-3.258</td>
<td>spi_u0/spi_clk_control_pos_s1/Q</td>
<td>spi_u0/spi_clk_control_s2/D</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]</td>
<td>0.159</td>
<td>0.359</td>
<td>2.628</td>
</tr>
<tr style="color: #FF0000;">
<td>6</td>
<td>-3.119</td>
<td>spi_u0/spi_dir_5_s0/Q</td>
<td>spi_u0/mem_rdata_5_s0/D</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.318</td>
<td>0.374</td>
<td>2.632</td>
</tr>
<tr style="color: #FF0000;">
<td>7</td>
<td>-2.994</td>
<td>spi_u0/spi_start_s1/Q</td>
<td>spi_u0/spi_state_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>3.256</td>
</tr>
<tr style="color: #FF0000;">
<td>8</td>
<td>-2.798</td>
<td>spi_u0/spi_start_s1/Q</td>
<td>spi_u0/spi_clk_control_pos_s1/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>3.060</td>
</tr>
<tr style="color: #FF0000;">
<td>9</td>
<td>-2.464</td>
<td>spi_u0/spi_dir_2_s0/Q</td>
<td>spi_u0/mem_rdata_2_s0/D</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.318</td>
<td>0.374</td>
<td>1.977</td>
</tr>
<tr style="color: #FF0000;">
<td>10</td>
<td>-2.397</td>
<td>spi_u0/spi_dir_1_s0/Q</td>
<td>spi_u0/mem_rdata_1_s0/D</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.318</td>
<td>0.374</td>
<td>1.910</td>
</tr>
<tr style="color: #FF0000;">
<td>11</td>
<td>-2.397</td>
<td>spi_u0/spi_dir_3_s0/Q</td>
<td>spi_u0/mem_rdata_3_s0/D</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.318</td>
<td>0.374</td>
<td>1.910</td>
</tr>
<tr style="color: #FF0000;">
<td>12</td>
<td>-2.397</td>
<td>spi_u0/spi_dir_6_s0/Q</td>
<td>spi_u0/mem_rdata_6_s0/D</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.318</td>
<td>0.374</td>
<td>1.910</td>
</tr>
<tr style="color: #FF0000;">
<td>13</td>
<td>-2.185</td>
<td>spi_u0/spi_dir_7_s0/Q</td>
<td>spi_u0/mem_rdata_7_s0/D</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.318</td>
<td>0.374</td>
<td>1.699</td>
</tr>
<tr style="color: #FF0000;">
<td>14</td>
<td>-2.123</td>
<td>spi_u0/spi_start_s1/Q</td>
<td>spi_u0/spi_shift_o_1_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>2.384</td>
</tr>
<tr style="color: #FF0000;">
<td>15</td>
<td>-2.111</td>
<td>spi_u0/spi_dir_4_s0/Q</td>
<td>spi_u0/mem_rdata_4_s0/D</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.318</td>
<td>0.374</td>
<td>1.625</td>
</tr>
<tr style="color: #FF0000;">
<td>16</td>
<td>-1.864</td>
<td>spi_u0/spi_start_s1/Q</td>
<td>spi_u0/spi_shift_o_2_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>2.125</td>
</tr>
<tr style="color: #FF0000;">
<td>17</td>
<td>-1.864</td>
<td>spi_u0/spi_start_s1/Q</td>
<td>spi_u0/spi_shift_o_3_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>2.125</td>
</tr>
<tr style="color: #FF0000;">
<td>18</td>
<td>-1.864</td>
<td>spi_u0/spi_start_s1/Q</td>
<td>spi_u0/spi_shift_o_4_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>2.125</td>
</tr>
<tr style="color: #FF0000;">
<td>19</td>
<td>-1.864</td>
<td>spi_u0/spi_start_s1/Q</td>
<td>spi_u0/spi_shift_o_5_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>2.125</td>
</tr>
<tr style="color: #FF0000;">
<td>20</td>
<td>-1.864</td>
<td>spi_u0/spi_start_s1/Q</td>
<td>spi_u0/spi_shift_o_6_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>2.125</td>
</tr>
<tr style="color: #FF0000;">
<td>21</td>
<td>-1.809</td>
<td>spi_u0/spi_start_s1/Q</td>
<td>spi_u0/spi_shift_o_0_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>2.070</td>
</tr>
<tr>
<td>22</td>
<td>9.903</td>
<td>picorv32_core/mem_mux_u1/select_0_s4/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_14_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>39.683</td>
<td>0.000</td>
<td>29.380</td>
</tr>
<tr>
<td>23</td>
<td>11.588</td>
<td>picorv32_core/mem_mux_u1/select_0_s4/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_1_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>39.683</td>
<td>0.000</td>
<td>27.694</td>
</tr>
<tr>
<td>24</td>
<td>11.693</td>
<td>picorv32_core/mem_mux_u1/select_0_s4/Q</td>
<td>picorv32_core/uart_debug_u1/response_data_14_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>39.683</td>
<td>0.000</td>
<td>27.590</td>
</tr>
<tr>
<td>25</td>
<td>11.700</td>
<td>picorv32_core/mem_mux_u1/select_0_s4/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_6_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>39.683</td>
<td>0.000</td>
<td>27.583</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.499</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_23_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/core_reg_core_reg_0_0_s/DI[23]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.585</td>
</tr>
<tr>
<td>2</td>
<td>0.502</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/core_reg_core_reg_0_0_s0/DI[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.588</td>
</tr>
<tr>
<td>3</td>
<td>0.550</td>
<td>u_hdmi/svo_tmds_2/dout_9_s0/Q</td>
<td>u_hdmi/tmds_serdes[2]/D9</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.565</td>
</tr>
<tr>
<td>4</td>
<td>0.556</td>
<td>picorv32_core/riscv32_alu_u1/instr_latch_23_s1/Q</td>
<td>picorv32_core/riscv32_alu_u1/i_type_imme_3_s4/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.571</td>
</tr>
<tr>
<td>5</td>
<td>0.583</td>
<td>picorv32_core/riscv32_alu_u1/instr_latch_20_s1/Q</td>
<td>picorv32_core/riscv32_alu_u1/i_type_imme_0_s4/RESET</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.598</td>
</tr>
<tr>
<td>6</td>
<td>0.708</td>
<td>spi_u0/spi_cnt_2_s0/Q</td>
<td>spi_u0/spi_cnt_2_s0/D</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>7</td>
<td>0.708</td>
<td>u_hdmi/vga_driver_u1/cnt_h_2_s0/Q</td>
<td>u_hdmi/vga_driver_u1/cnt_h_2_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>8</td>
<td>0.708</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_2_s0/Q</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_2_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>9</td>
<td>0.708</td>
<td>uart_memory_u1/overtime_0_s0/Q</td>
<td>uart_memory_u1/overtime_0_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>10</td>
<td>0.708</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0/Q</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>11</td>
<td>0.708</td>
<td>uart_memory_u1/uart_delay_cnt_10_s0/Q</td>
<td>uart_memory_u1/uart_delay_cnt_10_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>12</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/dpc_5_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/dpc_5_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>13</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/dpc_24_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/dpc_24_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>14</td>
<td>0.708</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/cnt_clk_7_s0/Q</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/cnt_clk_7_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>15</td>
<td>0.708</td>
<td>picorv32_core/uart_debug_u1/u_uart_recv/cnt_clk_2_s0/Q</td>
<td>picorv32_core/uart_debug_u1/u_uart_recv/cnt_clk_2_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>16</td>
<td>0.709</td>
<td>u_hdmi/svo_tmds_2/cnt_1_s1/Q</td>
<td>u_hdmi/svo_tmds_2/cnt_1_s1/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>17</td>
<td>0.709</td>
<td>u_hdmi/vga_driver_u1/cnt_v_2_s0/Q</td>
<td>u_hdmi/vga_driver_u1/cnt_v_2_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>18</td>
<td>0.709</td>
<td>u_hdmi/vga_driver_u1/cnt_v_7_s0/Q</td>
<td>u_hdmi/vga_driver_u1/cnt_v_7_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>19</td>
<td>0.709</td>
<td>spi_u0/mem_ready_s4/Q</td>
<td>spi_u0/mem_ready_s4/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>20</td>
<td>0.709</td>
<td>uart_memory_u1/u_uart_recv/state_3_s1/Q</td>
<td>uart_memory_u1/u_uart_recv/state_3_s1/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>21</td>
<td>0.709</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_0_s0/Q</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_0_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>22</td>
<td>0.709</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_4_s0/Q</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_4_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>23</td>
<td>0.709</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_5_s0/Q</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_5_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>24</td>
<td>0.709</td>
<td>uart_memory_u1/uart_delay_cnt_14_s0/Q</td>
<td>uart_memory_u1/uart_delay_cnt_14_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>25</td>
<td>0.709</td>
<td>picorv32_core/riscv32_alu_u1/dpc_4_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/dpc_4_s0/D</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;">
<td>1</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_clk_control_pos_s1/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>2</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_shift_o_0_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>3</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_shift_o_1_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>4</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_shift_o_2_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>5</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_shift_o_3_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>6</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_shift_o_4_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>7</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_shift_o_5_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>8</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_shift_o_6_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>9</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_shift_o_7_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>10</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_dir_0_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>11</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_dir_1_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>12</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_dir_2_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>13</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_dir_3_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>14</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_dir_4_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>15</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_dir_5_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>16</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_dir_6_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>17</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_dir_7_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>18</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_cnt_0_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>19</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_cnt_1_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>20</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_cnt_2_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr style="color: #FF0000;">
<td>21</td>
<td>-5.503</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_state_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>spi_u0/spi_clk_inter:[R]</td>
<td>0.317</td>
<td>-0.374</td>
<td>6.121</td>
</tr>
<tr>
<td>22</td>
<td>33.519</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/mem_ready_s4/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>39.683</td>
<td>0.000</td>
<td>6.121</td>
</tr>
<tr>
<td>23</td>
<td>33.519</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_start_s1/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>39.683</td>
<td>0.000</td>
<td>6.121</td>
</tr>
<tr>
<td>24</td>
<td>33.519</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_div_0_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>39.683</td>
<td>0.000</td>
<td>6.121</td>
</tr>
<tr>
<td>25</td>
<td>33.519</td>
<td>u_Reset_Sync/reset_cnt_2_s0/Q</td>
<td>spi_u0/spi_div_1_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>39.683</td>
<td>0.000</td>
<td>6.121</td>
</tr>
</table>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.559</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_0_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.574</td>
</tr>
<tr>
<td>2</td>
<td>0.843</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_6_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.858</td>
</tr>
<tr>
<td>3</td>
<td>0.843</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_7_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.858</td>
</tr>
<tr>
<td>4</td>
<td>0.843</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_8_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.858</td>
</tr>
<tr>
<td>5</td>
<td>0.843</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_9_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.858</td>
</tr>
<tr>
<td>6</td>
<td>0.843</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_10_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.858</td>
</tr>
<tr>
<td>7</td>
<td>0.843</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_11_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.858</td>
</tr>
<tr>
<td>8</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_1_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>9</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_2_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>10</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_3_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>11</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_4_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>12</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_5_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>13</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_12_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>14</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_13_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>15</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_14_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>16</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_15_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>17</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_16_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>18</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_17_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>19</td>
<td>1.107</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_18_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.122</td>
</tr>
<tr>
<td>20</td>
<td>1.107</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_19_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.122</td>
</tr>
<tr>
<td>21</td>
<td>1.107</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_20_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.122</td>
</tr>
<tr>
<td>22</td>
<td>1.107</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_21_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.122</td>
</tr>
<tr>
<td>23</td>
<td>1.107</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_22_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.122</td>
</tr>
<tr>
<td>24</td>
<td>1.107</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_23_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.122</td>
</tr>
<tr>
<td>25</td>
<td>1.127</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_24_s0/CLEAR</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.142</td>
</tr>
</table>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>8.356</td>
<td>9.606</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>spi_u0/spi_clk_inter</td>
<td>spi_u0/spi_state_s0</td>
</tr>
<tr>
<td>2</td>
<td>8.356</td>
<td>9.606</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>spi_u0/spi_clk_inter</td>
<td>spi_u0/spi_cnt_2_s0</td>
</tr>
<tr>
<td>3</td>
<td>8.356</td>
<td>9.606</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>spi_u0/spi_clk_inter</td>
<td>spi_u0/spi_shift_o_6_s0</td>
</tr>
<tr>
<td>4</td>
<td>8.356</td>
<td>9.606</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>spi_u0/spi_clk_inter</td>
<td>spi_u0/spi_shift_o_5_s0</td>
</tr>
<tr>
<td>5</td>
<td>8.356</td>
<td>9.606</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>spi_u0/spi_clk_inter</td>
<td>spi_u0/spi_shift_o_4_s0</td>
</tr>
<tr>
<td>6</td>
<td>8.356</td>
<td>9.606</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>spi_u0/spi_clk_inter</td>
<td>spi_u0/spi_shift_o_3_s0</td>
</tr>
<tr>
<td>7</td>
<td>8.356</td>
<td>9.606</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>spi_u0/spi_clk_inter</td>
<td>spi_u0/spi_shift_o_2_s0</td>
</tr>
<tr>
<td>8</td>
<td>8.356</td>
<td>9.606</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>spi_u0/spi_clk_inter</td>
<td>spi_u0/spi_shift_o_1_s0</td>
</tr>
<tr>
<td>9</td>
<td>8.356</td>
<td>9.606</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>spi_u0/spi_clk_inter</td>
<td>spi_u0/spi_shift_o_0_s0</td>
</tr>
<tr>
<td>10</td>
<td>8.356</td>
<td>9.606</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>spi_u0/spi_clk_inter</td>
<td>spi_u0/spi_clk_control_pos_s1</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.579</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2466.039</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2460.459</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_state_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/mem_rdata_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.000</td>
<td>2460.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>2460.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C31[1][A]</td>
<td>spi_u0/spi_state_s0/CLK</td>
</tr>
<tr>
<td>2461.404</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>24</td>
<td>R7C31[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_state_s0/Q</td>
</tr>
<tr>
<td>2465.007</td>
<td>3.603</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>spi_u0/n271_s8/I1</td>
</tr>
<tr>
<td>2466.039</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td style=" background: #97FFFF;">spi_u0/n271_s8/F</td>
</tr>
<tr>
<td>2466.039</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td style=" font-weight:bold;">spi_u0/mem_rdata_15_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.318</td>
<td>2460.318</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.318</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>2460.648</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>2460.890</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>spi_u0/mem_rdata_15_s0/CLK</td>
</tr>
<tr>
<td>2460.860</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/mem_rdata_15_s0</td>
</tr>
<tr>
<td>2460.460</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C16[2][B]</td>
<td>spi_u0/mem_rdata_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.318</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.032, 20.264%; route: 3.603, 70.737%; tC2Q: 0.458, 9.000%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.438</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>45.954</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.516</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_start_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C29[1][A]</td>
<td>spi_u0/spi_start_s1/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R13C29[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_start_s1/Q</td>
</tr>
<tr>
<td>41.140</td>
<td>0.427</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C29[3][A]</td>
<td>spi_u0/n104_s0/I0</td>
</tr>
<tr>
<td>42.239</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R12C29[3][A]</td>
<td style=" background: #97FFFF;">spi_u0/n104_s0/F</td>
</tr>
<tr>
<td>45.954</td>
<td>3.715</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT8[A]</td>
<td style=" font-weight:bold;">spi_u0/spi_shift_o_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT8[A]</td>
<td>spi_u0/spi_shift_o_7_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_shift_o_7_s0</td>
</tr>
<tr>
<td>40.516</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT8[A]</td>
<td>spi_u0/spi_shift_o_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 19.282%; route: 4.142, 72.676%; tC2Q: 0.458, 8.041%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.170</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2465.630</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2460.459</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_dir_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/mem_rdata_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.000</td>
<td>2460.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>2460.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT8[B]</td>
<td>spi_u0/spi_dir_0_s0/CLK</td>
</tr>
<tr>
<td>2461.404</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>IOT8[B]</td>
<td style=" font-weight:bold;">spi_u0/spi_dir_0_s0/Q</td>
</tr>
<tr>
<td>2464.808</td>
<td>3.404</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C31[0][A]</td>
<td>spi_u0/n286_s9/I1</td>
</tr>
<tr>
<td>2465.630</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C31[0][A]</td>
<td style=" background: #97FFFF;">spi_u0/n286_s9/F</td>
</tr>
<tr>
<td>2465.630</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C31[0][A]</td>
<td style=" font-weight:bold;">spi_u0/mem_rdata_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.318</td>
<td>2460.318</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.318</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>2460.648</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>2460.890</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C31[0][A]</td>
<td>spi_u0/mem_rdata_0_s0/CLK</td>
</tr>
<tr>
<td>2460.860</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/mem_rdata_0_s0</td>
</tr>
<tr>
<td>2460.460</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C31[0][A]</td>
<td>spi_u0/mem_rdata_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.318</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.822, 17.550%; route: 3.404, 72.665%; tC2Q: 0.458, 9.785%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.364</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2465.180</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2460.816</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_state_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_start_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.000</td>
<td>2460.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>2460.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C31[1][A]</td>
<td>spi_u0/spi_state_s0/CLK</td>
</tr>
<tr>
<td>2461.404</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>24</td>
<td>R7C31[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_state_s0/Q</td>
</tr>
<tr>
<td>2464.042</td>
<td>2.638</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C29[3][A]</td>
<td>spi_u0/spi_start_s3/I0</td>
</tr>
<tr>
<td>2464.844</td>
<td>0.802</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R13C29[3][A]</td>
<td style=" background: #97FFFF;">spi_u0/spi_start_s3/F</td>
</tr>
<tr>
<td>2465.180</td>
<td>0.336</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C29[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_start_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.318</td>
<td>2460.318</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.318</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>2460.648</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>2460.890</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C29[1][A]</td>
<td>spi_u0/spi_start_s1/CLK</td>
</tr>
<tr>
<td>2460.860</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_start_s1</td>
</tr>
<tr>
<td>2460.816</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C29[1][A]</td>
<td>spi_u0/spi_start_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.318</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.802, 18.941%; route: 2.974, 70.234%; tC2Q: 0.458, 10.825%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.258</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2483.574</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2480.316</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_clk_control_pos_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_clk_control_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2480.000</td>
<td>2480.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2480.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>2480.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>2480.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C31[2][A]</td>
<td>spi_u0/spi_clk_control_pos_s1/CLK</td>
</tr>
<tr>
<td>2481.404</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R7C31[2][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_clk_control_pos_s1/Q</td>
</tr>
<tr>
<td>2482.542</td>
<td>1.138</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C30[1][A]</td>
<td>spi_u0/n65_s0/I0</td>
</tr>
<tr>
<td>2483.574</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C30[1][A]</td>
<td style=" background: #97FFFF;">spi_u0/n65_s0/F</td>
</tr>
<tr>
<td>2483.574</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C30[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_clk_control_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2480.159</td>
<td>2480.159</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2480.159</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>2480.489</td>
<td>0.330</td>
<td>tCL</td>
<td>FF</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>2480.746</td>
<td>0.257</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C30[1][A]</td>
<td>spi_u0/spi_clk_control_s2/CLK</td>
</tr>
<tr>
<td>2480.716</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_control_s2</td>
</tr>
<tr>
<td>2480.316</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C30[1][A]</td>
<td>spi_u0/spi_clk_control_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.359</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.159</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.032, 39.268%; route: 1.138, 43.292%; tC2Q: 0.458, 17.440%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.257, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.119</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2463.578</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2460.459</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_dir_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/mem_rdata_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.000</td>
<td>2460.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>2460.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C29[2][A]</td>
<td>spi_u0/spi_dir_5_s0/CLK</td>
</tr>
<tr>
<td>2461.404</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R12C29[2][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_dir_5_s0/Q</td>
</tr>
<tr>
<td>2462.546</td>
<td>1.142</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C30[1][A]</td>
<td>spi_u0/n281_s9/I0</td>
</tr>
<tr>
<td>2463.578</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C30[1][A]</td>
<td style=" background: #97FFFF;">spi_u0/n281_s9/F</td>
</tr>
<tr>
<td>2463.578</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C30[1][A]</td>
<td style=" font-weight:bold;">spi_u0/mem_rdata_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.318</td>
<td>2460.318</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.318</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>2460.648</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>2460.890</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C30[1][A]</td>
<td>spi_u0/mem_rdata_5_s0/CLK</td>
</tr>
<tr>
<td>2460.860</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/mem_rdata_5_s0</td>
</tr>
<tr>
<td>2460.460</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C30[1][A]</td>
<td>spi_u0/mem_rdata_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.318</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.032, 39.207%; route: 1.142, 43.381%; tC2Q: 0.458, 17.413%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.994</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.510</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.516</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_start_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_state_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C29[1][A]</td>
<td>spi_u0/spi_start_s1/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>10</td>
<td>R13C29[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_start_s1/Q</td>
</tr>
<tr>
<td>42.688</td>
<td>1.975</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C31[1][A]</td>
<td>spi_u0/n95_s1/I1</td>
</tr>
<tr>
<td>43.510</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R7C31[1][A]</td>
<td style=" background: #97FFFF;">spi_u0/n95_s1/F</td>
</tr>
<tr>
<td>43.510</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C31[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_state_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C31[1][A]</td>
<td>spi_u0/spi_state_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_state_s0</td>
</tr>
<tr>
<td>40.516</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R7C31[1][A]</td>
<td>spi_u0/spi_state_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.822, 25.249%; route: 1.975, 60.673%; tC2Q: 0.458, 14.078%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.798</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>43.314</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.516</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_start_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_clk_control_pos_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C29[1][A]</td>
<td>spi_u0/spi_start_s1/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>10</td>
<td>R13C29[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_start_s1/Q</td>
</tr>
<tr>
<td>42.688</td>
<td>1.975</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C31[2][A]</td>
<td>spi_u0/n94_s1/I1</td>
</tr>
<tr>
<td>43.314</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R7C31[2][A]</td>
<td style=" background: #97FFFF;">spi_u0/n94_s1/F</td>
</tr>
<tr>
<td>43.314</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C31[2][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_clk_control_pos_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C31[2][A]</td>
<td>spi_u0/spi_clk_control_pos_s1/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_control_pos_s1</td>
</tr>
<tr>
<td>40.516</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R7C31[2][A]</td>
<td>spi_u0/spi_clk_control_pos_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.626, 20.460%; route: 1.975, 64.559%; tC2Q: 0.458, 14.980%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.464</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2462.923</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2460.459</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_dir_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/mem_rdata_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.000</td>
<td>2460.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>2460.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C30[2][A]</td>
<td>spi_u0/spi_dir_2_s0/CLK</td>
</tr>
<tr>
<td>2461.404</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R11C30[2][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_dir_2_s0/Q</td>
</tr>
<tr>
<td>2461.824</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C30[2][A]</td>
<td>spi_u0/n284_s9/I1</td>
</tr>
<tr>
<td>2462.923</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R12C30[2][A]</td>
<td style=" background: #97FFFF;">spi_u0/n284_s9/F</td>
</tr>
<tr>
<td>2462.923</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C30[2][A]</td>
<td style=" font-weight:bold;">spi_u0/mem_rdata_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.318</td>
<td>2460.318</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.318</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>2460.648</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>2460.890</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C30[2][A]</td>
<td>spi_u0/mem_rdata_2_s0/CLK</td>
</tr>
<tr>
<td>2460.860</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/mem_rdata_2_s0</td>
</tr>
<tr>
<td>2460.460</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C30[2][A]</td>
<td>spi_u0/mem_rdata_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.318</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 55.578%; route: 0.420, 21.244%; tC2Q: 0.458, 23.178%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.397</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2462.856</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2460.459</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_dir_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/mem_rdata_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.000</td>
<td>2460.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>2460.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C30[2][B]</td>
<td>spi_u0/spi_dir_1_s0/CLK</td>
</tr>
<tr>
<td>2461.404</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R11C30[2][B]</td>
<td style=" font-weight:bold;">spi_u0/spi_dir_1_s0/Q</td>
</tr>
<tr>
<td>2461.824</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C30[1][B]</td>
<td>spi_u0/n285_s9/I1</td>
</tr>
<tr>
<td>2462.856</td>
<td>1.032</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R12C30[1][B]</td>
<td style=" background: #97FFFF;">spi_u0/n285_s9/F</td>
</tr>
<tr>
<td>2462.856</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C30[1][B]</td>
<td style=" font-weight:bold;">spi_u0/mem_rdata_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.318</td>
<td>2460.318</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.318</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>2460.648</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>2460.890</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C30[1][B]</td>
<td>spi_u0/mem_rdata_1_s0/CLK</td>
</tr>
<tr>
<td>2460.860</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/mem_rdata_1_s0</td>
</tr>
<tr>
<td>2460.460</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C30[1][B]</td>
<td>spi_u0/mem_rdata_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.318</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.032, 54.020%; route: 0.420, 21.989%; tC2Q: 0.458, 23.991%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.397</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2462.856</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2460.459</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_dir_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/mem_rdata_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.000</td>
<td>2460.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>2460.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C29[1][A]</td>
<td>spi_u0/spi_dir_3_s0/CLK</td>
</tr>
<tr>
<td>2461.404</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R12C29[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_dir_3_s0/Q</td>
</tr>
<tr>
<td>2461.824</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C30[2][B]</td>
<td>spi_u0/n283_s9/I1</td>
</tr>
<tr>
<td>2462.856</td>
<td>1.032</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R12C30[2][B]</td>
<td style=" background: #97FFFF;">spi_u0/n283_s9/F</td>
</tr>
<tr>
<td>2462.856</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C30[2][B]</td>
<td style=" font-weight:bold;">spi_u0/mem_rdata_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.318</td>
<td>2460.318</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.318</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>2460.648</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>2460.890</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C30[2][B]</td>
<td>spi_u0/mem_rdata_3_s0/CLK</td>
</tr>
<tr>
<td>2460.860</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/mem_rdata_3_s0</td>
</tr>
<tr>
<td>2460.460</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C30[2][B]</td>
<td>spi_u0/mem_rdata_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.318</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.032, 54.020%; route: 0.420, 21.989%; tC2Q: 0.458, 23.991%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.397</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2462.856</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2460.459</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_dir_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/mem_rdata_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.000</td>
<td>2460.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>2460.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C30[2][A]</td>
<td>spi_u0/spi_dir_6_s0/CLK</td>
</tr>
<tr>
<td>2461.404</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C30[2][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_dir_6_s0/Q</td>
</tr>
<tr>
<td>2461.824</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C31[1][A]</td>
<td>spi_u0/n280_s9/I0</td>
</tr>
<tr>
<td>2462.856</td>
<td>1.032</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C31[1][A]</td>
<td style=" background: #97FFFF;">spi_u0/n280_s9/F</td>
</tr>
<tr>
<td>2462.856</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C31[1][A]</td>
<td style=" font-weight:bold;">spi_u0/mem_rdata_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.318</td>
<td>2460.318</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.318</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>2460.648</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>2460.890</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C31[1][A]</td>
<td>spi_u0/mem_rdata_6_s0/CLK</td>
</tr>
<tr>
<td>2460.860</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/mem_rdata_6_s0</td>
</tr>
<tr>
<td>2460.460</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C31[1][A]</td>
<td>spi_u0/mem_rdata_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.318</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.032, 54.020%; route: 0.420, 21.989%; tC2Q: 0.458, 23.991%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.185</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2462.645</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2460.459</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_dir_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/mem_rdata_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.000</td>
<td>2460.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>2460.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C30[2][B]</td>
<td>spi_u0/spi_dir_7_s0/CLK</td>
</tr>
<tr>
<td>2461.404</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R13C30[2][B]</td>
<td style=" font-weight:bold;">spi_u0/spi_dir_7_s0/Q</td>
</tr>
<tr>
<td>2461.823</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C29[0][A]</td>
<td>spi_u0/n279_s9/I0</td>
</tr>
<tr>
<td>2462.645</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C29[0][A]</td>
<td style=" background: #97FFFF;">spi_u0/n279_s9/F</td>
</tr>
<tr>
<td>2462.645</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C29[0][A]</td>
<td style=" font-weight:bold;">spi_u0/mem_rdata_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.318</td>
<td>2460.318</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.318</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>2460.648</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>2460.890</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C29[0][A]</td>
<td>spi_u0/mem_rdata_7_s0/CLK</td>
</tr>
<tr>
<td>2460.860</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/mem_rdata_7_s0</td>
</tr>
<tr>
<td>2460.460</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C29[0][A]</td>
<td>spi_u0/mem_rdata_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.318</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.822, 48.386%; route: 0.419, 24.635%; tC2Q: 0.458, 26.979%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.123</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.639</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.516</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_start_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C29[1][A]</td>
<td>spi_u0/spi_start_s1/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>10</td>
<td>R13C29[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_start_s1/Q</td>
</tr>
<tr>
<td>42.013</td>
<td>1.300</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C32[2][A]</td>
<td>spi_u0/n110_s0/I0</td>
</tr>
<tr>
<td>42.639</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C32[2][A]</td>
<td style=" background: #97FFFF;">spi_u0/n110_s0/F</td>
</tr>
<tr>
<td>42.639</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C32[2][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_shift_o_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C32[2][A]</td>
<td>spi_u0/spi_shift_o_1_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_shift_o_1_s0</td>
</tr>
<tr>
<td>40.516</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C32[2][A]</td>
<td>spi_u0/spi_shift_o_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.626, 26.257%; route: 1.300, 54.519%; tC2Q: 0.458, 19.224%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.111</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2462.571</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2460.459</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_dir_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/mem_rdata_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.000</td>
<td>2460.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>2460.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>2460.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C29[2][B]</td>
<td>spi_u0/spi_dir_4_s0/CLK</td>
</tr>
<tr>
<td>2461.404</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R12C29[2][B]</td>
<td style=" font-weight:bold;">spi_u0/spi_dir_4_s0/Q</td>
</tr>
<tr>
<td>2461.749</td>
<td>0.345</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C29[0][B]</td>
<td>spi_u0/n282_s9/I0</td>
</tr>
<tr>
<td>2462.571</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C29[0][B]</td>
<td style=" background: #97FFFF;">spi_u0/n282_s9/F</td>
</tr>
<tr>
<td>2462.571</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C29[0][B]</td>
<td style=" font-weight:bold;">spi_u0/mem_rdata_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>2460.318</td>
<td>2460.318</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>2460.318</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>2460.648</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>2460.890</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C29[0][B]</td>
<td>spi_u0/mem_rdata_4_s0/CLK</td>
</tr>
<tr>
<td>2460.860</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/mem_rdata_4_s0</td>
</tr>
<tr>
<td>2460.460</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C29[0][B]</td>
<td>spi_u0/mem_rdata_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.318</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.822, 50.583%; route: 0.345, 21.213%; tC2Q: 0.458, 28.204%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.864</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.380</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.516</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_start_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C29[1][A]</td>
<td>spi_u0/spi_start_s1/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>10</td>
<td>R13C29[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_start_s1/Q</td>
</tr>
<tr>
<td>41.558</td>
<td>0.845</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C31[0][A]</td>
<td>spi_u0/n109_s0/I0</td>
</tr>
<tr>
<td>42.380</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C31[0][A]</td>
<td style=" background: #97FFFF;">spi_u0/n109_s0/F</td>
</tr>
<tr>
<td>42.380</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C31[0][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_shift_o_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C31[0][A]</td>
<td>spi_u0/spi_shift_o_2_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_shift_o_2_s0</td>
</tr>
<tr>
<td>40.516</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C31[0][A]</td>
<td>spi_u0/spi_shift_o_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.822, 38.680%; route: 0.845, 39.753%; tC2Q: 0.458, 21.567%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.864</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.380</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.516</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_start_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C29[1][A]</td>
<td>spi_u0/spi_start_s1/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>10</td>
<td>R13C29[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_start_s1/Q</td>
</tr>
<tr>
<td>41.558</td>
<td>0.845</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C31[0][B]</td>
<td>spi_u0/n108_s0/I0</td>
</tr>
<tr>
<td>42.380</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C31[0][B]</td>
<td style=" background: #97FFFF;">spi_u0/n108_s0/F</td>
</tr>
<tr>
<td>42.380</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C31[0][B]</td>
<td style=" font-weight:bold;">spi_u0/spi_shift_o_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C31[0][B]</td>
<td>spi_u0/spi_shift_o_3_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_shift_o_3_s0</td>
</tr>
<tr>
<td>40.516</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C31[0][B]</td>
<td>spi_u0/spi_shift_o_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.822, 38.680%; route: 0.845, 39.753%; tC2Q: 0.458, 21.567%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.864</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.380</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.516</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_start_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C29[1][A]</td>
<td>spi_u0/spi_start_s1/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>10</td>
<td>R13C29[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_start_s1/Q</td>
</tr>
<tr>
<td>41.558</td>
<td>0.845</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C31[1][A]</td>
<td>spi_u0/n107_s0/I0</td>
</tr>
<tr>
<td>42.380</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C31[1][A]</td>
<td style=" background: #97FFFF;">spi_u0/n107_s0/F</td>
</tr>
<tr>
<td>42.380</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C31[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_shift_o_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C31[1][A]</td>
<td>spi_u0/spi_shift_o_4_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_shift_o_4_s0</td>
</tr>
<tr>
<td>40.516</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C31[1][A]</td>
<td>spi_u0/spi_shift_o_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.822, 38.680%; route: 0.845, 39.753%; tC2Q: 0.458, 21.567%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.864</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.380</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.516</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_start_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C29[1][A]</td>
<td>spi_u0/spi_start_s1/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>10</td>
<td>R13C29[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_start_s1/Q</td>
</tr>
<tr>
<td>41.558</td>
<td>0.845</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C31[1][B]</td>
<td>spi_u0/n106_s0/I0</td>
</tr>
<tr>
<td>42.380</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C31[1][B]</td>
<td style=" background: #97FFFF;">spi_u0/n106_s0/F</td>
</tr>
<tr>
<td>42.380</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C31[1][B]</td>
<td style=" font-weight:bold;">spi_u0/spi_shift_o_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C31[1][B]</td>
<td>spi_u0/spi_shift_o_5_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_shift_o_5_s0</td>
</tr>
<tr>
<td>40.516</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C31[1][B]</td>
<td>spi_u0/spi_shift_o_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.822, 38.680%; route: 0.845, 39.753%; tC2Q: 0.458, 21.567%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.864</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.380</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.516</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_start_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C29[1][A]</td>
<td>spi_u0/spi_start_s1/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>10</td>
<td>R13C29[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_start_s1/Q</td>
</tr>
<tr>
<td>41.558</td>
<td>0.845</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C31[2][A]</td>
<td>spi_u0/n105_s0/I0</td>
</tr>
<tr>
<td>42.380</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C31[2][A]</td>
<td style=" background: #97FFFF;">spi_u0/n105_s0/F</td>
</tr>
<tr>
<td>42.380</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C31[2][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_shift_o_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C31[2][A]</td>
<td>spi_u0/spi_shift_o_6_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_shift_o_6_s0</td>
</tr>
<tr>
<td>40.516</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C31[2][A]</td>
<td>spi_u0/spi_shift_o_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.822, 38.680%; route: 0.845, 39.753%; tC2Q: 0.458, 21.567%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-1.809</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.324</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.516</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_start_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C29[1][A]</td>
<td>spi_u0/spi_start_s1/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>10</td>
<td>R13C29[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_start_s1/Q</td>
</tr>
<tr>
<td>41.698</td>
<td>0.986</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C31[2][B]</td>
<td>spi_u0/n111_s1/I0</td>
</tr>
<tr>
<td>42.324</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C31[2][B]</td>
<td style=" background: #97FFFF;">spi_u0/n111_s1/F</td>
</tr>
<tr>
<td>42.324</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C31[2][B]</td>
<td style=" font-weight:bold;">spi_u0/spi_shift_o_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C31[2][B]</td>
<td>spi_u0/spi_shift_o_0_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_shift_o_0_s0</td>
</tr>
<tr>
<td>40.516</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C31[2][B]</td>
<td>spi_u0/spi_shift_o_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.626, 30.244%; route: 0.986, 47.613%; tC2Q: 0.458, 22.143%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>9.903</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>29.952</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>39.855</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/mem_mux_u1/select_0_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.572</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C29[1][A]</td>
<td>picorv32_core/mem_mux_u1/select_0_s4/CLK</td>
</tr>
<tr>
<td>1.030</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>108</td>
<td>R15C29[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/mem_mux_u1/select_0_s4/Q</td>
</tr>
<tr>
<td>6.134</td>
<td>5.104</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C27[2][A]</td>
<td>mem_ready_o_d_s11/I3</td>
</tr>
<tr>
<td>7.166</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R6C27[2][A]</td>
<td style=" background: #97FFFF;">mem_ready_o_d_s11/F</td>
</tr>
<tr>
<td>8.310</td>
<td>1.144</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C31[2][B]</td>
<td>mem_ready_o_d_s4/I2</td>
</tr>
<tr>
<td>8.936</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>80</td>
<td>R7C31[2][B]</td>
<td style=" background: #97FFFF;">mem_ready_o_d_s4/F</td>
</tr>
<tr>
<td>11.551</td>
<td>2.615</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n7011_s14/I3</td>
</tr>
<tr>
<td>12.650</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>20</td>
<td>R8C16[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n7011_s14/F</td>
</tr>
<tr>
<td>15.611</td>
<td>2.962</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C36[3][B]</td>
<td>picorv32_core/uart_debug_u1/n1789_s15/I1</td>
</tr>
<tr>
<td>16.710</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>70</td>
<td>R12C36[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/uart_debug_u1/n1789_s15/F</td>
</tr>
<tr>
<td>22.427</td>
<td>5.716</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C27[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n7009_s13/I0</td>
</tr>
<tr>
<td>23.526</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R11C27[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n7009_s13/F</td>
</tr>
<tr>
<td>26.773</td>
<td>3.248</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C8[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n7202_s8/I2</td>
</tr>
<tr>
<td>27.399</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C8[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n7202_s8/F</td>
</tr>
<tr>
<td>28.853</td>
<td>1.453</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C4[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n7202_s7/I1</td>
</tr>
<tr>
<td>29.952</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C4[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n7202_s7/F</td>
</tr>
<tr>
<td>29.952</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C4[2][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_wdata_14_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C4[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_14_s0/CLK</td>
</tr>
<tr>
<td>39.855</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C4[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>39.683</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.680, 22.737%; route: 22.241, 75.703%; tC2Q: 0.458, 1.560%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>11.588</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.266</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>39.855</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/mem_mux_u1/select_0_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.572</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C29[1][A]</td>
<td>picorv32_core/mem_mux_u1/select_0_s4/CLK</td>
</tr>
<tr>
<td>1.030</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>108</td>
<td>R15C29[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/mem_mux_u1/select_0_s4/Q</td>
</tr>
<tr>
<td>6.134</td>
<td>5.104</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C27[2][A]</td>
<td>mem_ready_o_d_s11/I3</td>
</tr>
<tr>
<td>7.166</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R6C27[2][A]</td>
<td style=" background: #97FFFF;">mem_ready_o_d_s11/F</td>
</tr>
<tr>
<td>8.310</td>
<td>1.144</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C31[2][B]</td>
<td>mem_ready_o_d_s4/I2</td>
</tr>
<tr>
<td>8.936</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>80</td>
<td>R7C31[2][B]</td>
<td style=" background: #97FFFF;">mem_ready_o_d_s4/F</td>
</tr>
<tr>
<td>11.551</td>
<td>2.615</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n7011_s14/I3</td>
</tr>
<tr>
<td>12.650</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>20</td>
<td>R8C16[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n7011_s14/F</td>
</tr>
<tr>
<td>15.611</td>
<td>2.962</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C36[3][B]</td>
<td>picorv32_core/uart_debug_u1/n1789_s15/I1</td>
</tr>
<tr>
<td>16.710</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>70</td>
<td>R12C36[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/uart_debug_u1/n1789_s15/F</td>
</tr>
<tr>
<td>22.101</td>
<td>5.391</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C11[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6998_s13/I0</td>
</tr>
<tr>
<td>22.923</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R8C11[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6998_s13/F</td>
</tr>
<tr>
<td>25.688</td>
<td>2.765</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C17[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n7215_s8/I1</td>
</tr>
<tr>
<td>26.749</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R8C17[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n7215_s8/F</td>
</tr>
<tr>
<td>27.167</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C18[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n7215_s7/I1</td>
</tr>
<tr>
<td>28.266</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R8C18[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n7215_s7/F</td>
</tr>
<tr>
<td>28.266</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C18[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_wdata_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C18[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_1_s0/CLK</td>
</tr>
<tr>
<td>39.855</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C18[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>39.683</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.838, 24.691%; route: 20.398, 73.654%; tC2Q: 0.458, 1.655%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>11.693</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.162</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>39.855</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/mem_mux_u1/select_0_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/uart_debug_u1/response_data_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.572</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C29[1][A]</td>
<td>picorv32_core/mem_mux_u1/select_0_s4/CLK</td>
</tr>
<tr>
<td>1.030</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>108</td>
<td>R15C29[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/mem_mux_u1/select_0_s4/Q</td>
</tr>
<tr>
<td>6.134</td>
<td>5.104</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C27[2][A]</td>
<td>mem_ready_o_d_s11/I3</td>
</tr>
<tr>
<td>7.166</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R6C27[2][A]</td>
<td style=" background: #97FFFF;">mem_ready_o_d_s11/F</td>
</tr>
<tr>
<td>8.310</td>
<td>1.144</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C31[2][B]</td>
<td>mem_ready_o_d_s4/I2</td>
</tr>
<tr>
<td>8.936</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>80</td>
<td>R7C31[2][B]</td>
<td style=" background: #97FFFF;">mem_ready_o_d_s4/F</td>
</tr>
<tr>
<td>11.551</td>
<td>2.615</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n7011_s14/I3</td>
</tr>
<tr>
<td>12.650</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>20</td>
<td>R8C16[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n7011_s14/F</td>
</tr>
<tr>
<td>15.611</td>
<td>2.962</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C36[3][B]</td>
<td>picorv32_core/uart_debug_u1/n1789_s15/I1</td>
</tr>
<tr>
<td>16.710</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>70</td>
<td>R12C36[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/uart_debug_u1/n1789_s15/F</td>
</tr>
<tr>
<td>22.427</td>
<td>5.716</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C27[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n7009_s13/I0</td>
</tr>
<tr>
<td>23.526</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R11C27[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n7009_s13/F</td>
</tr>
<tr>
<td>25.159</td>
<td>1.634</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C37[3][B]</td>
<td>picorv32_core/uart_debug_u1/n1801_s5/I1</td>
</tr>
<tr>
<td>26.258</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C37[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/uart_debug_u1/n1801_s5/F</td>
</tr>
<tr>
<td>27.063</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C37[0][B]</td>
<td>picorv32_core/uart_debug_u1/n1801_s3/I1</td>
</tr>
<tr>
<td>28.162</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C37[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/uart_debug_u1/n1801_s3/F</td>
</tr>
<tr>
<td>28.162</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C37[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/response_data_14_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C37[0][B]</td>
<td>picorv32_core/uart_debug_u1/response_data_14_s0/CLK</td>
</tr>
<tr>
<td>39.855</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C37[0][B]</td>
<td>picorv32_core/uart_debug_u1/response_data_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>39.683</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 7.153, 25.926%; route: 19.978, 72.412%; tC2Q: 0.458, 1.661%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>11.700</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.155</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>39.855</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/mem_mux_u1/select_0_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.572</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C29[1][A]</td>
<td>picorv32_core/mem_mux_u1/select_0_s4/CLK</td>
</tr>
<tr>
<td>1.030</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>108</td>
<td>R15C29[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/mem_mux_u1/select_0_s4/Q</td>
</tr>
<tr>
<td>6.134</td>
<td>5.104</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C27[2][A]</td>
<td>mem_ready_o_d_s11/I3</td>
</tr>
<tr>
<td>7.166</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R6C27[2][A]</td>
<td style=" background: #97FFFF;">mem_ready_o_d_s11/F</td>
</tr>
<tr>
<td>8.310</td>
<td>1.144</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C31[2][B]</td>
<td>mem_ready_o_d_s4/I2</td>
</tr>
<tr>
<td>8.936</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>80</td>
<td>R7C31[2][B]</td>
<td style=" background: #97FFFF;">mem_ready_o_d_s4/F</td>
</tr>
<tr>
<td>11.551</td>
<td>2.615</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n7011_s14/I3</td>
</tr>
<tr>
<td>12.650</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>20</td>
<td>R8C16[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n7011_s14/F</td>
</tr>
<tr>
<td>15.611</td>
<td>2.962</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C36[3][B]</td>
<td>picorv32_core/uart_debug_u1/n1789_s15/I1</td>
</tr>
<tr>
<td>16.710</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>70</td>
<td>R12C36[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/uart_debug_u1/n1789_s15/F</td>
</tr>
<tr>
<td>22.427</td>
<td>5.716</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C27[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n7009_s13/I0</td>
</tr>
<tr>
<td>23.526</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R11C27[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n7009_s13/F</td>
</tr>
<tr>
<td>26.289</td>
<td>2.763</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C10[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n7210_s8/I0</td>
</tr>
<tr>
<td>26.914</td>
<td>0.625</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R17C10[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n7210_s8/F</td>
</tr>
<tr>
<td>27.333</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C10[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n7210_s7/I0</td>
</tr>
<tr>
<td>28.155</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C10[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n7210_s7/F</td>
</tr>
<tr>
<td>28.155</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C10[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_wdata_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C10[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_6_s0/CLK</td>
</tr>
<tr>
<td>39.855</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C10[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>39.683</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.402, 23.210%; route: 20.722, 75.128%; tC2Q: 0.458, 1.662%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.499</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.098</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.599</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_23_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/core_reg_core_reg_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_23_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>R11C15[2][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_wdata_23_s0/Q</td>
</tr>
<tr>
<td>1.098</td>
<td>0.252</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R10[3]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/core_reg_core_reg_0_0_s/DI[23]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[3]</td>
<td>picorv32_core/riscv32_alu_u1/core_reg_core_reg_0_0_s/CLKA</td>
</tr>
<tr>
<td>0.599</td>
<td>0.086</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[3]</td>
<td>picorv32_core/riscv32_alu_u1/core_reg_core_reg_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.252, 43.029%; tC2Q: 0.333, 56.971%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.502</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.101</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.599</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/core_reg_core_reg_0_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C17[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_0_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>R11C17[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_wdata_0_s0/Q</td>
</tr>
<tr>
<td>1.101</td>
<td>0.254</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R10[4]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/core_reg_core_reg_0_0_s0/DI[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[4]</td>
<td>picorv32_core/riscv32_alu_u1/core_reg_core_reg_0_0_s0/CLKA</td>
</tr>
<tr>
<td>0.599</td>
<td>0.086</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[4]</td>
<td>picorv32_core/riscv32_alu_u1/core_reg_core_reg_0_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.254, 43.287%; tC2Q: 0.333, 56.713%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.550</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.078</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_hdmi/svo_tmds_2/dout_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/tmds_serdes[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C38[0][A]</td>
<td>u_hdmi/svo_tmds_2/dout_9_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R2C38[0][A]</td>
<td style=" font-weight:bold;">u_hdmi/svo_tmds_2/dout_9_s0/Q</td>
</tr>
<tr>
<td>1.078</td>
<td>0.231</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT38[A]</td>
<td style=" font-weight:bold;">u_hdmi/tmds_serdes[2]/D9</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT38[A]</td>
<td>u_hdmi/tmds_serdes[2]/PCLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOT38[A]</td>
<td>u_hdmi/tmds_serdes[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.231, 40.960%; tC2Q: 0.333, 59.040%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.556</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.084</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/instr_latch_23_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/i_type_imme_3_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C12[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/instr_latch_23_s1/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R5C12[2][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/instr_latch_23_s1/Q</td>
</tr>
<tr>
<td>1.084</td>
<td>0.238</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C12[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/i_type_imme_3_s4/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C12[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/i_type_imme_3_s4/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R5C12[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/i_type_imme_3_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.583</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.111</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/instr_latch_20_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/i_type_imme_0_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/instr_latch_20_s1/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R5C16[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/instr_latch_20_s1/Q</td>
</tr>
<tr>
<td>1.111</td>
<td>0.265</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C15[2][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/i_type_imme_0_s4/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C15[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/i_type_imme_0_s4/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R5C15[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/i_type_imme_0_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.265, 44.283%; tC2Q: 0.333, 55.717%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.391</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.684</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/spi_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_cnt_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>0.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C31[0][A]</td>
<td>spi_u0/spi_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.017</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R7C31[0][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_cnt_2_s0/Q</td>
</tr>
<tr>
<td>1.019</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C31[0][A]</td>
<td>spi_u0/n112_s1/I2</td>
</tr>
<tr>
<td>1.391</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R7C31[0][A]</td>
<td style=" background: #97FFFF;">spi_u0/n112_s1/F</td>
</tr>
<tr>
<td>1.391</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C31[0][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_cnt_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>0.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C31[0][A]</td>
<td>spi_u0/spi_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>0.684</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R7C31[0][A]</td>
<td>spi_u0/spi_cnt_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.684, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.684, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_hdmi/vga_driver_u1/cnt_h_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/vga_driver_u1/cnt_h_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C33[1][A]</td>
<td>u_hdmi/vga_driver_u1/cnt_h_2_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R3C33[1][A]</td>
<td style=" font-weight:bold;">u_hdmi/vga_driver_u1/cnt_h_2_s0/Q</td>
</tr>
<tr>
<td>0.849</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C33[1][A]</td>
<td>u_hdmi/vga_driver_u1/n87_s1/I3</td>
</tr>
<tr>
<td>1.221</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R3C33[1][A]</td>
<td style=" background: #97FFFF;">u_hdmi/vga_driver_u1/n87_s1/F</td>
</tr>
<tr>
<td>1.221</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C33[1][A]</td>
<td style=" font-weight:bold;">u_hdmi/vga_driver_u1/cnt_h_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C33[1][A]</td>
<td>u_hdmi/vga_driver_u1/cnt_h_2_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R3C33[1][A]</td>
<td>u_hdmi/vga_driver_u1/cnt_h_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C33[1][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_2_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C33[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/cnt_clk_2_s0/Q</td>
</tr>
<tr>
<td>0.849</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C33[1][A]</td>
<td>uart_memory_u1/u_uart_recv/n85_s1/I3</td>
</tr>
<tr>
<td>1.221</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C33[1][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/u_uart_recv/n85_s1/F</td>
</tr>
<tr>
<td>1.221</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C33[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/cnt_clk_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C33[1][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_2_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C33[1][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[0][A]</td>
<td>uart_memory_u1/overtime_0_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R17C31[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_0_s0/Q</td>
</tr>
<tr>
<td>0.849</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[0][A]</td>
<td>uart_memory_u1/n135_s2/I0</td>
</tr>
<tr>
<td>1.221</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R17C31[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n135_s2/F</td>
</tr>
<tr>
<td>1.221</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C31[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[0][A]</td>
<td>uart_memory_u1/overtime_0_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C31[0][A]</td>
<td>uart_memory_u1/overtime_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C32[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R23C32[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_3_s0/Q</td>
</tr>
<tr>
<td>0.849</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C32[0][A]</td>
<td>uart_memory_u1/n53_s3/I1</td>
</tr>
<tr>
<td>1.221</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R23C32[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n53_s3/F</td>
</tr>
<tr>
<td>1.221</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C32[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C32[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R23C32[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_delay_cnt_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_delay_cnt_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C30[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_10_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R25C30[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_10_s0/Q</td>
</tr>
<tr>
<td>0.849</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C30[0][A]</td>
<td>uart_memory_u1/n46_s4/I1</td>
</tr>
<tr>
<td>1.221</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R25C30[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n46_s4/F</td>
</tr>
<tr>
<td>1.221</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R25C30[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_10_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C30[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_10_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R25C30[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/dpc_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/dpc_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C21[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/dpc_5_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R4C21[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/dpc_5_s0/Q</td>
</tr>
<tr>
<td>0.849</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C21[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n7083_s8/I1</td>
</tr>
<tr>
<td>1.221</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R4C21[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n7083_s8/F</td>
</tr>
<tr>
<td>1.221</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C21[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/dpc_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C21[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/dpc_5_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C21[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/dpc_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/dpc_24_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/dpc_24_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C25[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/dpc_24_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R4C25[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/dpc_24_s0/Q</td>
</tr>
<tr>
<td>0.849</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C25[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n7064_s8/I1</td>
</tr>
<tr>
<td>1.221</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R4C25[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n7064_s8/F</td>
</tr>
<tr>
<td>1.221</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C25[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/dpc_24_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C25[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/dpc_24_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C25[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/dpc_24_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/cnt_clk_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/cnt_clk_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C34[0][A]</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/cnt_clk_7_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R25C34[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/u_uart_txd/cnt_clk_7_s0/Q</td>
</tr>
<tr>
<td>0.849</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C34[0][A]</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/n116_s1/I2</td>
</tr>
<tr>
<td>1.221</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R25C34[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/uart_debug_u1/u_uart_txd/n116_s1/F</td>
</tr>
<tr>
<td>1.221</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R25C34[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/u_uart_txd/cnt_clk_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C34[0][A]</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/cnt_clk_7_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R25C34[0][A]</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/cnt_clk_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.221</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/u_uart_recv/cnt_clk_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/uart_debug_u1/u_uart_recv/cnt_clk_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C39[0][A]</td>
<td>picorv32_core/uart_debug_u1/u_uart_recv/cnt_clk_2_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R23C39[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/u_uart_recv/cnt_clk_2_s0/Q</td>
</tr>
<tr>
<td>0.849</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C39[0][A]</td>
<td>picorv32_core/uart_debug_u1/u_uart_recv/n85_s1/I3</td>
</tr>
<tr>
<td>1.221</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R23C39[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/uart_debug_u1/u_uart_recv/n85_s1/F</td>
</tr>
<tr>
<td>1.221</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C39[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/u_uart_recv/cnt_clk_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C39[0][A]</td>
<td>picorv32_core/uart_debug_u1/u_uart_recv/cnt_clk_2_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R23C39[0][A]</td>
<td>picorv32_core/uart_debug_u1/u_uart_recv/cnt_clk_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.222</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_hdmi/svo_tmds_2/cnt_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/svo_tmds_2/cnt_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C41[0][A]</td>
<td>u_hdmi/svo_tmds_2/cnt_1_s1/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R5C41[0][A]</td>
<td style=" font-weight:bold;">u_hdmi/svo_tmds_2/cnt_1_s1/Q</td>
</tr>
<tr>
<td>0.850</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C41[0][A]</td>
<td>u_hdmi/svo_tmds_2/n366_s4/I0</td>
</tr>
<tr>
<td>1.222</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R5C41[0][A]</td>
<td style=" background: #97FFFF;">u_hdmi/svo_tmds_2/n366_s4/F</td>
</tr>
<tr>
<td>1.222</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C41[0][A]</td>
<td style=" font-weight:bold;">u_hdmi/svo_tmds_2/cnt_1_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C41[0][A]</td>
<td>u_hdmi/svo_tmds_2/cnt_1_s1/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R5C41[0][A]</td>
<td>u_hdmi/svo_tmds_2/cnt_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.222</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_hdmi/vga_driver_u1/cnt_v_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/vga_driver_u1/cnt_v_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C33[1][A]</td>
<td>u_hdmi/vga_driver_u1/cnt_v_2_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>7</td>
<td>R5C33[1][A]</td>
<td style=" font-weight:bold;">u_hdmi/vga_driver_u1/cnt_v_2_s0/Q</td>
</tr>
<tr>
<td>0.850</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C33[1][A]</td>
<td>u_hdmi/vga_driver_u1/n130_s3/I1</td>
</tr>
<tr>
<td>1.222</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R5C33[1][A]</td>
<td style=" background: #97FFFF;">u_hdmi/vga_driver_u1/n130_s3/F</td>
</tr>
<tr>
<td>1.222</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C33[1][A]</td>
<td style=" font-weight:bold;">u_hdmi/vga_driver_u1/cnt_v_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C33[1][A]</td>
<td>u_hdmi/vga_driver_u1/cnt_v_2_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R5C33[1][A]</td>
<td>u_hdmi/vga_driver_u1/cnt_v_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.222</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_hdmi/vga_driver_u1/cnt_v_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_hdmi/vga_driver_u1/cnt_v_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C34[0][A]</td>
<td>u_hdmi/vga_driver_u1/cnt_v_7_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R4C34[0][A]</td>
<td style=" font-weight:bold;">u_hdmi/vga_driver_u1/cnt_v_7_s0/Q</td>
</tr>
<tr>
<td>0.850</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C34[0][A]</td>
<td>u_hdmi/vga_driver_u1/n125_s1/I2</td>
</tr>
<tr>
<td>1.222</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R4C34[0][A]</td>
<td style=" background: #97FFFF;">u_hdmi/vga_driver_u1/n125_s1/F</td>
</tr>
<tr>
<td>1.222</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C34[0][A]</td>
<td style=" font-weight:bold;">u_hdmi/vga_driver_u1/cnt_v_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C34[0][A]</td>
<td>u_hdmi/vga_driver_u1/cnt_v_7_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C34[0][A]</td>
<td>u_hdmi/vga_driver_u1/cnt_v_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.222</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>spi_u0/mem_ready_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/mem_ready_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C33[0][A]</td>
<td>spi_u0/mem_ready_s4/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R11C33[0][A]</td>
<td style=" font-weight:bold;">spi_u0/mem_ready_s4/Q</td>
</tr>
<tr>
<td>0.850</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C33[0][A]</td>
<td>spi_u0/n148_s2/I0</td>
</tr>
<tr>
<td>1.222</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C33[0][A]</td>
<td style=" background: #97FFFF;">spi_u0/n148_s2/F</td>
</tr>
<tr>
<td>1.222</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C33[0][A]</td>
<td style=" font-weight:bold;">spi_u0/mem_ready_s4/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C33[0][A]</td>
<td>spi_u0/mem_ready_s4/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C33[0][A]</td>
<td>spi_u0/mem_ready_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.222</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/u_uart_recv/state_3_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/state_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C32[0][A]</td>
<td>uart_memory_u1/u_uart_recv/state_3_s1/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R21C32[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/state_3_s1/Q</td>
</tr>
<tr>
<td>0.850</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C32[0][A]</td>
<td>uart_memory_u1/u_uart_recv/n68_s1/I1</td>
</tr>
<tr>
<td>1.222</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C32[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/u_uart_recv/n68_s1/F</td>
</tr>
<tr>
<td>1.222</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/state_3_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C32[0][A]</td>
<td>uart_memory_u1/u_uart_recv/state_3_s1/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C32[0][A]</td>
<td>uart_memory_u1/u_uart_recv/state_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.222</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[0][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_0_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R20C33[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/cnt_clk_0_s0/Q</td>
</tr>
<tr>
<td>0.850</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[0][A]</td>
<td>uart_memory_u1/u_uart_recv/n87_s2/I0</td>
</tr>
<tr>
<td>1.222</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R20C33[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/u_uart_recv/n87_s2/F</td>
</tr>
<tr>
<td>1.222</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C33[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/cnt_clk_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[0][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_0_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C33[0][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.222</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C31[0][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_4_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R21C31[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/cnt_clk_4_s0/Q</td>
</tr>
<tr>
<td>0.850</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C31[0][A]</td>
<td>uart_memory_u1/u_uart_recv/n83_s1/I3</td>
</tr>
<tr>
<td>1.222</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C31[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/u_uart_recv/n83_s1/F</td>
</tr>
<tr>
<td>1.222</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C31[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/cnt_clk_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C31[0][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_4_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C31[0][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.222</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_5_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R20C33[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/cnt_clk_5_s0/Q</td>
</tr>
<tr>
<td>0.850</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][A]</td>
<td>uart_memory_u1/u_uart_recv/n82_s1/I2</td>
</tr>
<tr>
<td>1.222</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R20C33[1][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/u_uart_recv/n82_s1/F</td>
</tr>
<tr>
<td>1.222</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C33[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/cnt_clk_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[1][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_5_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C33[1][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.222</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_delay_cnt_14_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_delay_cnt_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C31[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_14_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R23C31[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_14_s0/Q</td>
</tr>
<tr>
<td>0.850</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C31[1][A]</td>
<td>uart_memory_u1/n42_s3/I0</td>
</tr>
<tr>
<td>1.222</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R23C31[1][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n42_s3/F</td>
</tr>
<tr>
<td>1.222</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C31[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_14_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C31[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_14_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R23C31[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.222</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.513</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/dpc_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/dpc_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C27[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/dpc_4_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R3C27[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/dpc_4_s0/Q</td>
</tr>
<tr>
<td>0.850</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C27[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n7084_s8/I1</td>
</tr>
<tr>
<td>1.222</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R3C27[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n7084_s8/F</td>
</tr>
<tr>
<td>1.222</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C27[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/dpc_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C27[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/dpc_4_s0/CLK</td>
</tr>
<tr>
<td>0.513</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R3C27[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/dpc_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_clk_control_pos_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C31[2][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_clk_control_pos_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C31[2][A]</td>
<td>spi_u0/spi_clk_control_pos_s1/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_control_pos_s1</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R7C31[2][A]</td>
<td>spi_u0/spi_clk_control_pos_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C31[2][B]</td>
<td style=" font-weight:bold;">spi_u0/spi_shift_o_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C31[2][B]</td>
<td>spi_u0/spi_shift_o_0_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_shift_o_0_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C31[2][B]</td>
<td>spi_u0/spi_shift_o_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C32[2][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_shift_o_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C32[2][A]</td>
<td>spi_u0/spi_shift_o_1_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_shift_o_1_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C32[2][A]</td>
<td>spi_u0/spi_shift_o_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C31[0][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_shift_o_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C31[0][A]</td>
<td>spi_u0/spi_shift_o_2_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_shift_o_2_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C31[0][A]</td>
<td>spi_u0/spi_shift_o_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C31[0][B]</td>
<td style=" font-weight:bold;">spi_u0/spi_shift_o_3_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C31[0][B]</td>
<td>spi_u0/spi_shift_o_3_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_shift_o_3_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C31[0][B]</td>
<td>spi_u0/spi_shift_o_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C31[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_shift_o_4_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C31[1][A]</td>
<td>spi_u0/spi_shift_o_4_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_shift_o_4_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C31[1][A]</td>
<td>spi_u0/spi_shift_o_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C31[1][B]</td>
<td style=" font-weight:bold;">spi_u0/spi_shift_o_5_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C31[1][B]</td>
<td>spi_u0/spi_shift_o_5_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_shift_o_5_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C31[1][B]</td>
<td>spi_u0/spi_shift_o_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C31[2][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_shift_o_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C31[2][A]</td>
<td>spi_u0/spi_shift_o_6_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_shift_o_6_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C31[2][A]</td>
<td>spi_u0/spi_shift_o_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_shift_o_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT8[A]</td>
<td style=" font-weight:bold;">spi_u0/spi_shift_o_7_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT8[A]</td>
<td>spi_u0/spi_shift_o_7_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_shift_o_7_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT8[A]</td>
<td>spi_u0/spi_shift_o_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_dir_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT8[B]</td>
<td style=" font-weight:bold;">spi_u0/spi_dir_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT8[B]</td>
<td>spi_u0/spi_dir_0_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_dir_0_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT8[B]</td>
<td>spi_u0/spi_dir_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_dir_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C30[2][B]</td>
<td style=" font-weight:bold;">spi_u0/spi_dir_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C30[2][B]</td>
<td>spi_u0/spi_dir_1_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_dir_1_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C30[2][B]</td>
<td>spi_u0/spi_dir_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_dir_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C30[2][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_dir_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C30[2][A]</td>
<td>spi_u0/spi_dir_2_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_dir_2_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C30[2][A]</td>
<td>spi_u0/spi_dir_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_dir_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C29[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_dir_3_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C29[1][A]</td>
<td>spi_u0/spi_dir_3_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_dir_3_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C29[1][A]</td>
<td>spi_u0/spi_dir_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_dir_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C29[2][B]</td>
<td style=" font-weight:bold;">spi_u0/spi_dir_4_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C29[2][B]</td>
<td>spi_u0/spi_dir_4_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_dir_4_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C29[2][B]</td>
<td>spi_u0/spi_dir_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_dir_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C29[2][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_dir_5_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C29[2][A]</td>
<td>spi_u0/spi_dir_5_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_dir_5_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C29[2][A]</td>
<td>spi_u0/spi_dir_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_dir_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C30[2][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_dir_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C30[2][A]</td>
<td>spi_u0/spi_dir_6_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_dir_6_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C30[2][A]</td>
<td>spi_u0/spi_dir_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_dir_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C30[2][B]</td>
<td style=" font-weight:bold;">spi_u0/spi_dir_7_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C30[2][B]</td>
<td>spi_u0/spi_dir_7_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_dir_7_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C30[2][B]</td>
<td>spi_u0/spi_dir_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_cnt_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C32[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_cnt_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C32[1][A]</td>
<td>spi_u0/spi_cnt_0_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_cnt_0_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R6C32[1][A]</td>
<td>spi_u0/spi_cnt_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_cnt_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C31[1][B]</td>
<td style=" font-weight:bold;">spi_u0/spi_cnt_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C31[1][B]</td>
<td>spi_u0/spi_cnt_1_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_cnt_1_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R7C31[1][B]</td>
<td>spi_u0/spi_cnt_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_cnt_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C31[0][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_cnt_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C31[0][A]</td>
<td>spi_u0/spi_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_cnt_2_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R7C31[0][A]</td>
<td>spi_u0/spi_cnt_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>46.375</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_state_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>spi_u0/spi_clk_inter:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>40.713</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>42.494</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>43.593</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>46.375</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C31[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_state_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>21</td>
<td>R11C28[2][B]</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>40.946</td>
<td>0.946</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C31[1][A]</td>
<td>spi_u0/spi_state_s0/CLK</td>
</tr>
<tr>
<td>40.916</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>spi_u0/spi_state_s0</td>
</tr>
<tr>
<td>40.873</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R7C31[1][A]</td>
<td>spi_u0/spi_state_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.374</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>0.317</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.946, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>33.519</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.693</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.211</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/mem_ready_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.572</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.030</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>2.811</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>3.910</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>6.693</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C33[0][A]</td>
<td style=" font-weight:bold;">spi_u0/mem_ready_s4/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C33[0][A]</td>
<td>spi_u0/mem_ready_s4/CLK</td>
</tr>
<tr>
<td>40.211</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C33[0][A]</td>
<td>spi_u0/mem_ready_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>39.683</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>33.519</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.693</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.211</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_start_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.572</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.030</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>2.811</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>3.910</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>6.693</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C29[1][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_start_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C29[1][A]</td>
<td>spi_u0/spi_start_s1/CLK</td>
</tr>
<tr>
<td>40.211</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C29[1][A]</td>
<td>spi_u0/spi_start_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>39.683</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>33.519</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.693</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.211</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_div_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.572</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.030</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>2.811</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>3.910</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>6.693</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C31[2][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_div_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C31[2][A]</td>
<td>spi_u0/spi_div_0_s0/CLK</td>
</tr>
<tr>
<td>40.211</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C31[2][A]</td>
<td>spi_u0/spi_div_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>39.683</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>33.519</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.693</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.211</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_Reset_Sync/reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_u0/spi_div_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.572</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C33[1][A]</td>
<td>u_Reset_Sync/reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.030</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>3</td>
<td>R16C33[1][A]</td>
<td style=" font-weight:bold;">u_Reset_Sync/reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>2.811</td>
<td>1.781</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C33[2][A]</td>
<td>n325_s2/I2</td>
</tr>
<tr>
<td>3.910</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>523</td>
<td>R16C33[2][A]</td>
<td style=" background: #97FFFF;">n325_s2/F</td>
</tr>
<tr>
<td>6.693</td>
<td>2.782</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C30[0][A]</td>
<td style=" font-weight:bold;">spi_u0/spi_div_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>39.683</td>
<td>39.683</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>39.683</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>40.013</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>40.255</td>
<td>0.242</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C30[0][A]</td>
<td>spi_u0/spi_div_1_s0/CLK</td>
</tr>
<tr>
<td>40.211</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C30[0][A]</td>
<td>spi_u0/spi_div_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>39.683</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 17.956%; route: 4.563, 74.556%; tC2Q: 0.458, 7.488%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.242, 100.000%</td>
</tr>
</table>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.559</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.088</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.088</td>
<td>0.241</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[0][A]</td>
<td>uart_memory_u1/overtime_0_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C31[0][A]</td>
<td>uart_memory_u1/overtime_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.241, 41.973%; tC2Q: 0.333, 58.027%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.371</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.371</td>
<td>0.525</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C33[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C33[0][A]</td>
<td>uart_memory_u1/overtime_6_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C33[0][A]</td>
<td>uart_memory_u1/overtime_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.525, 61.156%; tC2Q: 0.333, 38.844%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.371</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.371</td>
<td>0.525</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C33[0][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_7_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C33[0][B]</td>
<td>uart_memory_u1/overtime_7_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C33[0][B]</td>
<td>uart_memory_u1/overtime_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.525, 61.156%; tC2Q: 0.333, 38.844%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.371</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.371</td>
<td>0.525</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C33[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_8_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C33[1][A]</td>
<td>uart_memory_u1/overtime_8_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C33[1][A]</td>
<td>uart_memory_u1/overtime_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.525, 61.156%; tC2Q: 0.333, 38.844%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.371</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.371</td>
<td>0.525</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C33[1][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_9_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C33[1][B]</td>
<td>uart_memory_u1/overtime_9_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C33[1][B]</td>
<td>uart_memory_u1/overtime_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.525, 61.156%; tC2Q: 0.333, 38.844%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.371</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.371</td>
<td>0.525</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C33[2][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_10_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C33[2][A]</td>
<td>uart_memory_u1/overtime_10_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C33[2][A]</td>
<td>uart_memory_u1/overtime_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.525, 61.156%; tC2Q: 0.333, 38.844%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.371</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.371</td>
<td>0.525</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C33[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_11_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C33[2][B]</td>
<td>uart_memory_u1/overtime_11_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C33[2][B]</td>
<td>uart_memory_u1/overtime_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.525, 61.156%; tC2Q: 0.333, 38.844%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.429</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.429</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C32[0][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C32[0][B]</td>
<td>uart_memory_u1/overtime_1_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C32[0][B]</td>
<td>uart_memory_u1/overtime_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.429</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.429</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C32[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C32[1][A]</td>
<td>uart_memory_u1/overtime_2_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C32[1][A]</td>
<td>uart_memory_u1/overtime_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.429</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.429</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C32[1][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_3_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C32[1][B]</td>
<td>uart_memory_u1/overtime_3_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C32[1][B]</td>
<td>uart_memory_u1/overtime_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.429</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.429</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C32[2][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_4_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C32[2][A]</td>
<td>uart_memory_u1/overtime_4_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C32[2][A]</td>
<td>uart_memory_u1/overtime_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.429</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.429</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C32[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_5_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C32[2][B]</td>
<td>uart_memory_u1/overtime_5_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C32[2][B]</td>
<td>uart_memory_u1/overtime_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.429</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.429</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_12_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[0][A]</td>
<td>uart_memory_u1/overtime_12_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C34[0][A]</td>
<td>uart_memory_u1/overtime_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.429</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.429</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[0][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_13_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[0][B]</td>
<td>uart_memory_u1/overtime_13_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C34[0][B]</td>
<td>uart_memory_u1/overtime_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.429</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.429</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_14_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[1][A]</td>
<td>uart_memory_u1/overtime_14_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C34[1][A]</td>
<td>uart_memory_u1/overtime_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.429</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.429</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[1][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_15_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[1][B]</td>
<td>uart_memory_u1/overtime_15_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C34[1][B]</td>
<td>uart_memory_u1/overtime_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.429</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_16_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.429</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[2][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_16_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[2][A]</td>
<td>uart_memory_u1/overtime_16_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C34[2][A]</td>
<td>uart_memory_u1/overtime_16_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.429</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_17_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.429</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_17_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C34[2][B]</td>
<td>uart_memory_u1/overtime_17_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C34[2][B]</td>
<td>uart_memory_u1/overtime_17_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.107</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.635</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_18_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.635</td>
<td>0.789</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C35[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_18_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C35[0][A]</td>
<td>uart_memory_u1/overtime_18_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C35[0][A]</td>
<td>uart_memory_u1/overtime_18_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.789, 70.288%; tC2Q: 0.333, 29.712%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.107</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.635</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_19_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.635</td>
<td>0.789</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C35[0][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_19_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C35[0][B]</td>
<td>uart_memory_u1/overtime_19_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C35[0][B]</td>
<td>uart_memory_u1/overtime_19_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.789, 70.288%; tC2Q: 0.333, 29.712%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.107</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.635</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_20_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.635</td>
<td>0.789</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C35[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_20_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C35[1][A]</td>
<td>uart_memory_u1/overtime_20_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C35[1][A]</td>
<td>uart_memory_u1/overtime_20_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.789, 70.288%; tC2Q: 0.333, 29.712%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.107</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.635</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_21_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.635</td>
<td>0.789</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C35[1][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_21_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C35[1][B]</td>
<td>uart_memory_u1/overtime_21_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C35[1][B]</td>
<td>uart_memory_u1/overtime_21_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.789, 70.288%; tC2Q: 0.333, 29.712%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.107</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.635</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_22_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.635</td>
<td>0.789</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C35[2][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_22_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C35[2][A]</td>
<td>uart_memory_u1/overtime_22_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C35[2][A]</td>
<td>uart_memory_u1/overtime_22_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.789, 70.288%; tC2Q: 0.333, 29.712%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.107</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.635</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_23_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.635</td>
<td>0.789</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C35[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_23_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C35[2][B]</td>
<td>uart_memory_u1/overtime_23_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C35[2][B]</td>
<td>uart_memory_u1/overtime_23_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.789, 70.288%; tC2Q: 0.333, 29.712%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.127</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.655</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.528</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_24_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C31[2][B]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>29</td>
<td>R17C31[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.655</td>
<td>0.808</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C36[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_24_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.330</td>
<td>0.330</td>
<td>tCL</td>
<td>RR</td>
<td>1271</td>
<td>TOPSIDE[0]</td>
<td>u_div_5/clkdiv_inst/CLKOUT</td>
</tr>
<tr>
<td>0.513</td>
<td>0.183</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C36[0][A]</td>
<td>uart_memory_u1/overtime_24_s0/CLK</td>
</tr>
<tr>
<td>0.528</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C36[0][A]</td>
<td>uart_memory_u1/overtime_24_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.808, 70.805%; tC2Q: 0.333, 29.195%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.183, 100.000%</td>
</tr>
</table>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.356</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.606</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>spi_u0/spi_state_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>11.078</td>
<td>1.078</td>
<td>tNET</td>
<td>FF</td>
<td>spi_u0/spi_state_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>20.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>spi_u0/spi_state_s0/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.356</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.606</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>spi_u0/spi_cnt_2_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>11.078</td>
<td>1.078</td>
<td>tNET</td>
<td>FF</td>
<td>spi_u0/spi_cnt_2_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>20.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>spi_u0/spi_cnt_2_s0/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.356</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.606</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>spi_u0/spi_shift_o_6_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>11.078</td>
<td>1.078</td>
<td>tNET</td>
<td>FF</td>
<td>spi_u0/spi_shift_o_6_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>20.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>spi_u0/spi_shift_o_6_s0/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.356</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.606</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>spi_u0/spi_shift_o_5_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>11.078</td>
<td>1.078</td>
<td>tNET</td>
<td>FF</td>
<td>spi_u0/spi_shift_o_5_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>20.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>spi_u0/spi_shift_o_5_s0/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.356</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.606</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>spi_u0/spi_shift_o_4_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>11.078</td>
<td>1.078</td>
<td>tNET</td>
<td>FF</td>
<td>spi_u0/spi_shift_o_4_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>20.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>spi_u0/spi_shift_o_4_s0/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.356</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.606</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>spi_u0/spi_shift_o_3_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>11.078</td>
<td>1.078</td>
<td>tNET</td>
<td>FF</td>
<td>spi_u0/spi_shift_o_3_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>20.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>spi_u0/spi_shift_o_3_s0/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.356</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.606</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>spi_u0/spi_shift_o_2_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>11.078</td>
<td>1.078</td>
<td>tNET</td>
<td>FF</td>
<td>spi_u0/spi_shift_o_2_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>20.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>spi_u0/spi_shift_o_2_s0/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.356</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.606</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>spi_u0/spi_shift_o_1_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>11.078</td>
<td>1.078</td>
<td>tNET</td>
<td>FF</td>
<td>spi_u0/spi_shift_o_1_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>20.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>spi_u0/spi_shift_o_1_s0/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.356</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.606</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>spi_u0/spi_shift_o_0_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>11.078</td>
<td>1.078</td>
<td>tNET</td>
<td>FF</td>
<td>spi_u0/spi_shift_o_0_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>20.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>spi_u0/spi_shift_o_0_s0/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.356</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.606</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>spi_u0/spi_clk_control_pos_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>11.078</td>
<td>1.078</td>
<td>tNET</td>
<td>FF</td>
<td>spi_u0/spi_clk_control_pos_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>spi_u0/spi_clk_inter</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>spi_u0/spi_clk_inter_s1/F</td>
</tr>
<tr>
<td>20.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>spi_u0/spi_clk_control_pos_s1/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>1271</td>
<td>clk_p</td>
<td>-5.503</td>
<td>0.659</td>
</tr>
<tr>
<td>523</td>
<td>n325_7</td>
<td>-5.503</td>
<td>2.782</td>
</tr>
<tr>
<td>466</td>
<td>cpu_state[1]</td>
<td>23.089</td>
<td>7.653</td>
</tr>
<tr>
<td>170</td>
<td>cpu_state[2]</td>
<td>23.884</td>
<td>6.703</td>
</tr>
<tr>
<td>134</td>
<td>cpu_state[0]</td>
<td>24.109</td>
<td>5.934</td>
</tr>
<tr>
<td>111</td>
<td>uart_state[0]</td>
<td>29.387</td>
<td>3.302</td>
</tr>
<tr>
<td>108</td>
<td>n7057_16</td>
<td>20.723</td>
<td>6.386</td>
</tr>
<tr>
<td>108</td>
<td>select[0]</td>
<td>9.903</td>
<td>6.557</td>
</tr>
<tr>
<td>91</td>
<td>op2num[2]</td>
<td>15.285</td>
<td>4.735</td>
</tr>
<tr>
<td>86</td>
<td>n2522_15</td>
<td>19.580</td>
<td>7.047</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R8C20</td>
<td>94.44%</td>
</tr>
<tr>
<td>R15C21</td>
<td>93.06%</td>
</tr>
<tr>
<td>R23C24</td>
<td>91.67%</td>
</tr>
<tr>
<td>R24C22</td>
<td>91.67%</td>
</tr>
<tr>
<td>R9C12</td>
<td>91.67%</td>
</tr>
<tr>
<td>R15C19</td>
<td>91.67%</td>
</tr>
<tr>
<td>R15C22</td>
<td>91.67%</td>
</tr>
<tr>
<td>R12C13</td>
<td>90.28%</td>
</tr>
<tr>
<td>R7C11</td>
<td>90.28%</td>
</tr>
<tr>
<td>R14C17</td>
<td>90.28%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
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